1. Field
An embodiment of the present invention relates to the field of integrated circuits and, more particularly to a low voltage swing reducer circuit such as a 3 to 2 reducer.
2. Discussion of Related Art
Reducer circuits reduce a first number of input signals to a second smaller number of output signals. 3 to 2 reducer circuits, for example, receive three vectors, perform a local bit wise sum and carry generation, and provide the resulting SUM and CARRY vectors as outputs. Typically, if each of the input vectors is a 32-bit vector, for example, 32 3 to 2 reducer circuits are used to perform the reduction and produce the resulting SUM and CARRY vectors. Thus, a 3 to 2 reducer that receives input vectors X, Y and Z operates according to the following equations:
SUM(i)=X(i)XOR Y(i)XOR Z(i)
CARRY(i)=X(i)*Y(i)+Y(i)*Z(i)+X(i)*Z(i)
where i is the particular bit of the vector being evaluated, xe2x80x98+xe2x80x99 indicates a logical OR function and xe2x80x98*xe2x80x99 indicates a logical AND function.
Reducer circuits are widely used in digital design to reduce the number of vectors to be added. Where many vectors are to be added, multiple 3 to 2 reducer circuits, for example, may be cascaded. To cascade two 3 to 2 reducers, the CARRY output of a first 3 to 2 reducer is left-shifted and provided as an input to a second 3 to 2 reducer. The SUM output of the first 3 to 2 reducer and a new vector are also provided to the second 3 to 2 reducer. The second 3 to 2 reducer then produces SUM and CARRY output signals based on the input vectors.
Prior 3 to 2 reducer circuits have typically been implemented in static complementary metal oxide semiconductor (CMOS) logic. As shown in FIG. 6, a typical static CMOS implementation uses at least two stages (because the XOR function is not straightforward in static CMOS) and thus, may involve multiple gate delays. Where multiple 3 to 2 reducers are cascaded, with the high-speed requirements of today""s integrated circuit devices, such a delay may be unacceptable. Further, static CMOS logic may consume an undesirable amount of area and power.
Additionally, if the input vectors to either single or cascaded 3 to 2 reducers arrive at different times, the design may become unduly complicated.
In accordance with one aspect of the invention, an apparatus includes a first number of input terminals including at least two input terminals coupled to receive a differential, small swing signal. A reducer circuit to generate differential, small swing sum and carry output signals based on data received via the input terminals is also included.